AVX — An Instroduction
instruction set was announced by Intel in March of 2008. It departs from Intel's usual instruction encoding form in that it allows 3-operand instructions.
It's also intended to address growing register sized in the future, as SIMD widths increase. Initially, plans are for 16 256-bit registers, but it also extends to 512-bit registers with AVX-512. Whereas SSE registers are called XMM0-XMM7, AVX's registers
are called YMM0-YMM15. The XMM registers map to the bottom half of each of the larger YMM registers.
AVX repurposes many SSE
instructions, and also adds the following:
- Copies a 32-128 bit operand to all fields of a register.
- Replaces the top or bottom half of a YMM register
- Copies the top or bottom half of a YMM register
- Conditional move
- "In-Lane" shuffle (can't shuffle across 128-bit boundaries).
- Shuffles 2 sources into a single destination.
- Sets all YMM registers to zero.
- Clears the top half of all YMM registers.