Streaming SIMD Extensions 3 (SSE3)
SSE3 — An Overview
SSE3 was introduced by Intel
in early 2004 with their
Prescott revision of the Pentium 4 CPU. SSE3 adds only 13 new instructions, but allows for
new features such as horizontal operation (operating across a single register instead of
down through multiple registers) and some unaligned access instructions. There are also a
couple process control instructions to boost performance with Intel's HyperThreading
started supporting SSE3 in April of 2005, and omitted the
instructions, which are only useful for HyperThreading CPUs.
SSE3 — OpCode List(under construction - need pictures :)
addsubpd - Adds the top two doubles and subtracts the bottom two.
addsubps - Adds top singles and subtracts bottom singles.
haddpd - Top double is sum of top and bottom, bottom double is sum of second operand's top and
haddps - Horizontal addition of single-precision values.
hsubpd - Horizontal subtraction of double-precision values.
hsubps - Horizontal subtraction of single-precision values.
lddqu - Loads an unaligned 128bit value.
movddup - Loads 64bits and duplicates it in the top and bottom halves of a 128bit register.
movshdup - Duplicates the high singles into high and low singles.
movsldup - Duplicates the low singles into high and low singles.
fisttp - Converts a floating-point value to an integer using truncation.
monitor - Sets up a region to monitor for activity.
mwait - Waits until activity happens in a region
SSE3 — See AlsoIntel
Documentation on SSE3 Instructions.