# Supplemental Streaming SIMD Extensions 3 (SSE3)

## SSSE3 — An Introduction

With Intel's Core 2 architecture, a few new instructiosn were added to the SSE3 collection. These were mistakenly called SSE4 at times while
under development, and are also known as Tejas New Instructiosn (TNI), or Merom New Instructions (MNI). It includes 16 new instructions

## SSSE3 — The Instructions

`psignd`

- Gives 32bit integer magnitudes the sign of the 2nd operand.

`psignw`

- Gives 16bit integer magnitudes the sign of the 2nd operand.

`psignb`

- Gives 8bit integer magnitudes the sign of the 2nd operand.

`phaddd`

- Horizontal addition of unsigned 32bit integers.

`phaddw`

- Horizontal addition of unsigned 16bit integers.

`phaddsw`

- Horizontal saturated addition of 16bit integers.

`phsubd`

- Horizontal subtraction of unsigned 32bit integers.

`phsubw`

- Horizontal subtraction of unsigned 16bit integers.

`phsubsw`

- Horizontal saturated subtraction of 16bit words.

`pmaddubsw`

- Multiply-accumulate instruction (finally).

`pabsd`

- `abs()`

for 32bit integers.

`pabsw`

- `abs()`

for 16bit integers.

`pabsb`

- `abs()`

for 8bit integers.

`pmulhrsw`

- 16bit integer multiplication, stores top 16bits of result.

`pshufb`

- Another complex shuffle instruction.

`palignr`

- Combines two register values, and extracts a register-width value from it, based on an offset.